Burst-mode clock and data recovery in optical multiaccess networks using broad-band PLLs

Design of High-speed Burst Mode Clock and Data Recovery IC for Passive Optical Network

Design of a high bit rate burst mode clock and data recovery (BMCDR) circuit for gigabit passive optical networks (GPON) is described. A top-down design flow is established and some of the key issues related to the behavioural level modeling are addressed in consideration for the complexity of the BMCDR integrated circuit (IC). Precise implementation of Simulink behavioural model accounting for...

Theory of Burst-Mode Receiver and its Applications in Optical Multiaccess Networks - Lightwave Technology, Journal of

In this paper, a unified theory for the newly developed optical burst-mode receiver is presented. Based on this theory, an analysis of the performance of the receiver is given both theoretically and experimentally. The theoretical model agrees well with the experimental results. This theory can quantitatively explain the bit error rate (BER) performance of burst-mode receivers. Several potentia...

A 1.25-Gb/s Burst-Mode Half-Rate Clock and Data Recovery Circuit Using Realigned Oscillation

In this letter, a 1.25-Gb/s 0.18-μm CMOS half-rate burstmode clock and data recovery (CDR) circuit is presented. The CDR contains a fast-locking clock recovery circuit (CRC) using a realigned oscillation technique to recover the desired clock. To reduce the power dissipation, the CRC uses a two-stage ring structure and a current-reused concept to merge with an edge detector. The recovered clock...

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With 4× Oversampling

1.25/2.5-Gb/s Dual Bit-Rate Burst-Mode Clock Recovery Circuit Using Gated-Oscillators

A burst-mode clock recovery circuit with a novel dual-mode structure is presented. It utilizes two gated-oscillators to align recovered clock edges to data. It can operate in double data-rate mode in which both rising and falling edges of recovered clock are used. To enable this, gated-oscillator reset-phase control scheme is introduced to switch the starting phase of gated-oscillator dynamical...